Presently, a memory device such as, for example, multi-level cell (MLC) flash memory may include individual multi-level cells (MLCs) that may be programmed to multiple voltage levels. For example, a 2-bit per cell NAND device may include cells that start at an erased voltage level (L0) and may be programmed to one of three program voltage levels (L1, L2 or L3). Such programming may occur in a series of loops where each loop includes only a single program pulse. A programming time for the MLCs may correspond with a number of loops and operations (e.g., program, verify, etc.) performed during the loops. The ongoing demand for faster operation of memory may drive reduction of the programming time in MLC memory devices.